Question

g: virtual memory uses a page table to track the mapping of virtual addresses to physical addresses. this excise shows how this table must be updated as addresses are accessed. the following data constitutes a stream of virtual addresses as seen on a system. assume 4 kib pages, a 4-entry fully associative tlb, and true lru replacement. if pages must be brought in from disk, increment the next largest page number. virtual address decimal 4669 2227 13916 34587 48870 12608 49225 hex 0x123d 0x08b3 0x365c 0x871b 0xbee6 0x3140 0xc049 tlb valid tag physical page number time since last access 1 11 12 4 1 7 4 1 1 3 6 3 0 4 9 7 page table index valid physical page or in disk 0 1 5 1 0 disk 2 0 disk 3 1 6 4 1 9 5 1 11 6 0 disk 7 1 4 8 0 disk 9 0 disk a 1 3 b 1 12 for each access shown in the address table, list a. whether the access is a hit or miss in the tlb b. whether the access is a hit or miss in the page table c. whether the access is a page fault d. the updated state of the tlb

Answer 1

This exercise involves managing a TLB and page table in a virtual memory system to track virtual-to-physical address mappings, handling TLB hits/misses, page table hits/misses, and page faults according to an LRU replacement policy.

Step-by-step explanation:

The exercise involves managing a Translation Lookaside Buffer (TLB) and a page table in a virtual memory system. Virtual addresses are mapped to physical addresses using these data structures, with considerations for page faults, TLB hits and misses, and page replacement strategies.

• a. TLB Hit or Miss: This is determined by whether the virtual page number from the address is currently stored in the TLB.
• b. Page Table Hit or Miss: If the TLB misses, but the virtual page number is in the page table with a valid bit, this is a page table hit.
• c. Page Fault: Occurs if the requested page is not in memory (i.e., not in the page table or it is there but marked as not valid).
• d. Updated State of the TLB: After each memory access, the TLB must be updated according to the access outcome and the LRU replacement policy if needed.

1. Access to virtual address 4669 (0x123D): We use the page number by dividing the address by 4 KiB, which is address/4096. This results in page number 1, which is a TLB miss as the tag 1 does not exist in the TLB. However, checking the page table, we can see it is a page table hit (physical page 5) with no page fault. The TLB is updated with this page, replacing the LRU entry.
2. Access to virtual address 2227 (0x08B3): Again, divide by 4096 to find the page number. This results in page number 0, which is a TLB miss. Moreover, page 0 is on disk as per the page table, so it is a page fault. A new page (next largest page number, which we'll assume is 13 since the highest we see is 12) is brought into memory and updated in the TLB and page table.
3. The process is repeated for the rest of the addresses, updating the TLB and the page table based on the outcomes of the TLB and page table hits/misses and page faults as per the scenario described.

Answer 2

Access in TLB and page table, page fault and TLB update

Step-by-step explanation:

a. The access is a miss in the TLB if the valid bit for the corresponding entry is 0 or if the tags in the TLB do not match the virtual address. Otherwise, it is a hit in the TLB.

b. If the access is a miss in the TLB, then it is also a miss in the page table, as TLB is checked first for translation. Otherwise, if the access is a hit in the TLB, it may or may not be a hit in the page table, depending on whether the valid bit for the corresponding entry is 1 or 0.

c. If an access is a miss in both the TLB and page table, it is a page fault and the corresponding page needs to be brought in from disk.

d. The TLB is updated after each access by either replacing an entry using the true LRU policy or inserting a new entry if there is a miss in the TLB. The updated state of the TLB is not given in the question, so it can't be determined. However, new entries may have been inserted or existing entries may have been replaced based on the TLB access behavior.