Question

Consider a pipelined than can issue up to one instruction per cycle, but fewer may be issued because of pipeline hazards, multi-cycle latency ALU operations and memory access to slower memories. It has a clock speed of 3.2Ghz. It executes a program with 1.8 billion instructions in 1.4 seconds, devoting 90% of the CPU's time to the program. What was the actual achieved issue rate of instructions per cycle?

Answer 1

Achieved Instruction per cycle rate is
`4.11* 10^(15)`

Solution:

As per the question:

Execution time, t = 1.4 s

No. of instructions being executed, n = 1.8 billion =

Clock speed of CPU, f = 3.2 GHz =
`3.2* 10^(9) Hz`

Now, to calculate the actual issue rate achieved:

CPI (Cycle per Instruction) =
`(t)/(n* f)`

CPI =
`(1.4)/(1.8* 10^(6)* 3.2* 10^(9))`

Instruction per cycle is given as the reciprocal of CPI:

Instruction per cycle =
`(1.8* 10^(6)* 3.2* 10^(9))/(1.4) = 4.11* 10^(15)`